Conventional data processing systems such as image data processors require extensive hardware to perform a series of arithmetic logic operations on the data. For example, image data requires the operations of image acquisition, spatial filtering, temporal filtering, histogram equalization, image display, to name just a few. Each such operation requires a separate hardware implementation in separate boards or separate gate arrays. Such implementations are expensive and are relatively inefficient in the sense that while all the necessary hardware is always present it is being utilized only a small part of the time during the period when its particular operation in the series is called for. The hardware actually involves two components: an address generator for selecting the pixel addresses in the sequence called for by the operation, and an arithmetic logic unit, which actually performs the operation on the sequenced data.
The escalation of hardware required is even greater in pipeline systems, which feature fixed image data banks. A pipeline system is one in which a number of image processing operations are being performed on a number of different frames of pixels as the frames are shifted through the pipeline or a series of processors. In one variety of pipeline system where the image data is fixed and does not move through the pipeline, each frame must be serviced by a sequence of address generators and associated arithmetic logic units; that requires two large multiplexer switches with massive switching capability to connect the right pair of address generators and arithmetic logic units to each frame in the proper sequence.